As is known in the art, in microwave analog circuits in general, and in power amplifiers specifically, an Output Matching Network (OMN), comprising passive components (capacitors, inductors, resistors, transmission lines and other distributed circuit elements) is used to transform an external circuit load impedance, ZL, (often equal to 50 Ohm) at one of its Radio Frequency (RF) output ports to a specific complex impedance at its input port as shown in FIG. 1. The input port is connected to an RF output of an active device, for example, the drain terminal in a common-source Field Effect Transistor (FET) or collector terminal in a common-emitter Bipolar Junction Transistor (BJT). The specific complex impedance presented by the OMN to the active device is selected to maximize one or several of its performance parameters; e.g., output power density, efficiency, linearity etc. Thus, OMN is connected between the output of a transistor used to amplify an input signal, and the external load for the purpose of providing a proper impedance transformation to: maximize the gain of the amplifier, or maximize the power provided by the amplifier to the external load, or maximize the efficiency of the amplifier, or maximize the linearity of the amplifier, for example.
More particularly, as is also known, the active device is generally coupled to a Direct Current (DC) supply, for example a bias drain voltage supply for a common-source FET, or a collector bias voltage source for a common-emitter BJT. Thus, the OMN is often required to block DC current from flowing between the bias voltage source and the RF output. Further, the OMN is required to, as noted above, perform an impedance transformation between the output of the active device and the input to the load with the least amount of signal being dissipated within the network (e.g. OMN loss needs to be minimized), so the overall circuit performance is dominated by that of the active device. Thus, in addition to the DC blocking, a part of the matching network's impedance transformation is sometimes accomplished by a predetermined shunt capacitance located in a close proximity to the DC-blocking series capacitor. Thus, in order to provide the required DC blocking and the required shunt capacitance, the OMN may include a DC blocking capacitor and a shunt capacitor section having a DC blocking capacitor and a shunt capacitor located in a close proximity to each other.
One integrated circuit implementation for the DC blocking capacitor and a shunt capacitor section of the OMN is shown in FIGS. 1A-1C. Here, a substrate has formed thereon a semiconductor disposed in a first portion of a top surface of the substrate and a ground plane conductor on a bottom surface of the substrate. The output matching network includes an input transmission line disposed over the substrate for coupling to: the output of a transistor device formed in the semiconductor layer; and a bias terminal for connection to a (DC) bias voltage source. An output input transmission line disposed over the substrate having an output adapted for coupling to a load. A series DC blocking capacitor is formed over one surface portion of the substrate. The bottom plate of the series capacitor is connected to the upper plate of the shunt capacitor through a portion of an output transmission line that overlays a portion of the upper plate and an air bridge conductor, as shown. The bottom plate of the shunt capacitor is connected to an underling portion the ground plane conductor through a conductive through-substrate via, as shown. It is noted that a parasitic capacitance between the bottom plate of the series capacitor and an underling portion of the ground plane conductor contributes a small fraction of the total shunt capacitance required for the OMN in the transformation of the impedance at the output to the transistor to the load. Thus, to obtain the required total shunt capacitance a separate lumped shunt capacitor is provided, as shown. It is noted that a parasitic capacitance between the bottom plate of the series capacitor and an underling portion of the ground plane conductor contributes to the total shunt capacitance of the OMN's DC blocking capacitor/Shunt capacitor section.
The performance of a small shunt capacitor is often very sensitive to process variations (thin-film dielectric thickness, lithography resolution). Its loss, and as a result the overall OMN loss is typically larger in comparison to the loss of its distributed equivalents because of higher dielectric loss tangent of thin-film insulating material The interconnect between separate series and shunt capacitors often requires to be reactively compensated, and also increases the OMN loss.
Another integrated circuit implementation for the DC blocking capacitor and a shunt capacitor section of the OMN is shown in FIGS. 2A-2C as distributed components. As noted above, a parasitic capacitance between the bottom plate of the series capacitor and an underling portion of the ground plane conductor contributes a fraction, typically a small one, of the total shunt capacitance required for the OMN in the transformation of the impedance at the output to the transistor to the load. Thus, to obtain the required total shunt capacitance a separate distributed shunt capacitor is provided, as shown. Here, the series capacitor and the shunt capacitor are formed over different surface portions of the substrate. The bottom plate of the series capacitor is connected to the upper plate of the shunt capacitor through a portion of an output transmission line that overlays a portion of the upper plate. Here, a portion of the output transmission line is connected to a section of a transmission line having a length selected to provide an open circuit transmission line stub, as shown. The open-circuit transmission line stub has surface area selected to provide the upper plate of the shunt capacitor. The bottom plate of the shunt capacitor is provided by an underling portion of the ground plane conductor.
The implementation in FIGS. 2A-C with the distributed implementation for the shunt capacitor occupies a larger chip area in comparison with the implementation in FIGS. 1A-C because of much thicker dielectric. The interconnection between separate series and shunt capacitors often requires to be reactively compensated, and also increases the OMN loss.